loopgen user manual
نویسنده
چکیده
The loopgen IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants) adhering to a common I/O interface, namely hwlu, a mixed-level structural/RTL architecture, ixgenb, a behavioral-level and ixgenr, a high-performance, pure RTL description of a more generalized form of the architecture. Hardware looping architectures have potential uses for data-intensive processing in embedded systems. The implemented architectures are able to provide all necessary control means for executing perfect loop nests without any cycle overhead for updating the iteration vector. Actually, successive last iterations of nested loops are performed in a single cycle. Such architectures can be used for implementing zero-cycle overhead loop controllers for perfect loop nests operating on multi-dimensional data. The following sections provide details on the contents of the delivered IP cores, which include all necessary materials such as source files and scripts for RTL simulation and logic synthesis. Reference documentation for LOOPGEN can be found in the /doc subdirectory in plain text, HTML and PDF form.
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